This invention relates to clocking conversion in communication systems, and more particularly relates to converting data clocked within a first speed range to data clocked within a higher speed range or within the same speed range.
Many applications in digital communication systems require converting a slower input clock rate to a higher system clock rate to increase performance. When two independent clocks are present in a design or system, there will always be an unknown phase difference between the two clock sources. When the independent clocks operate at different frequencies, the frequency difference will cause the clocks to move in both time and phase relationship to each other. Traditionally data synchronization in such systems requires extra memory in the form of an asynchronous FIFO or a ping-pong buffer with complex control logic. This invention addresses these deficiencies of the traditional approaches and provides a solution.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.